TDC Integratation in Ring-Oscillator PLLs
Master’s Thesis
For my master’s thesis, I am designing a TDC integrated into a Ring-ocillator PLL for fast, accurate, and PVT stable timing measurements. The circuit will be implemented in a 65 nm CMOS process. Alongside the thesis part I am also working on a conferance paper for the project in collaboration with my supervisors.
The project should cover the full IC design cycle — from architecture and schematic design to layout, verification, tape-out preparation, and post-silicon testing. Including noise and linearity optimization, switchable signal paths, biasing networks, and layout techniques for matching and low-noise performance.